Aporva Amarnath



Aporva Amarnath is a Ph.D. candidate at the University of Michigan. She is a part of the Circuits and Architecture Design Research (CADRe) group. Her advisor is Prof. Ronald Dreslinski.

Her research interests lie in building efficient computer architectures and systems for emerging non-Si CMOS technologies.

Work Experience

Advanced Micro Devices, May - Aug 2018
Architecture Research Co-op Engineer,
Worked on the PathForward project with the goal to enhance performance, reduce energy cost per instruction and lower performance variability per thread for exascale workloads. Optmized the power efficiency and memory-level parallelism of the Load-Store Unit (LS) design. Targeted improving performance by partitioning the load queue based on the state of load instructions. Designed an architectural mechanism to reduce dynamic power by reducing the associative searches done in the load and store queues.

NVIDIA Corporation, Jul 2014 - Jun 2015
Memory Design Co-op Intern,
Using Monte Carlo simulations on HSpice, designed and incorporated Advanced On-Chip Variation (AOCV) characterization module for timing enclosure into NanoTime reports for the SRAM design team. Published keeper-to-pull down rule for FINFETs based on writability of local read bitline and leakage and charge sharing supported by the keeper using Solido.

Research Projects

A new design framework for high-variation carbon-nanotube based transistor technology
Designed a multigranular-reconfigurable 3D architecture, used along with a CNT density variation model to improve yield and performance of high-variation CNTFETs.
Submitted to Design, Automation and Test in Europe (DATE), 2019.

A Reconfigurable Architecture for Addressing the Reliability Concerns of 3D Multi-Core Processors and Low Yield Rates of Future Technologies
Designed a fine-grained reconfigurable 3D architecture policy that detects faults on-line, repairs the system and decelerates aging caused by NBTI effects at a marginal clock cycle and area overhead.
Submitted to International Symposium on High-Performance Computer Architecture (HPCA), 2019.

OuterSPACE: An Outer product based SPArse matrix multiplication acCElerator
Designed an outer-product based matrix multiplication energy-efficient accelerator, which minimizes data movement and maximizes reuse to efficiently process billions of edges of real world matrices.

DARPA's Circuit Realization At Faster Timescales (CRAFT) Project
Built an advanced node chip as a part of a multi-university group for DARPA's CRAFT project aiming to minimize chip design time.

A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic
Explored circuit and architectural design choices using Carbon Nanotube field-effect transistor in pass transistor logic to create an energy-efficient RISC-V based processor.

Teaching Experience

EECS 470 (Computer Architecture), University of Michigan
  • Graduate student instructor for a 45-student course
  • Responsible for conducting lab sessions and office hours and assisting the Lecturer, Dr. Mark Brehob.
  • Responsible for grading final projects of students which involves building an entire out-of-order processor with special features to improve performance such as superscalar, multi-core and simultaneous multi-threading.

Publications

A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic
Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G Dreslinski
ISLPED 2017

Celerity: An Open Source RISC-V Tiered Accelerator Fabric
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G Dreslinski, Ian Galton, Rajesh K Gupta, Patrick P Mercier, Mani Srivastava, Michael B Taylor, Zhiru Zhang
Hot Chips 2017

Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Shaolin Xie, Chun Zhao, Ritchie Zhao
CARRV, Workshop in MICRO 2017

OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator
Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David Blaauw, Trevor Mudge, Ronald Dreslinski
HPCA 2018

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawai, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K Gupta, Zhiru Zhang, Ronald Dreslinski, Christopher Batten, Michael Bedford Taylor
IEEE MICRO Journal, 2018

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