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Abstract State Machines

Subjects

Methodology

Applications

ASM Studies

VHDL'93

Citation: Egon Börger, Uwe Glässer, and Wolfgang Muller, "Formal Definition of an Abstract VHDL'93 Simulator By EA-Machines", in C. Delgado Kloos and P.T. Breuer, eds., Formal Semantics for VHDL, Kluwer Academic Publishers, 1995, pp. 107-139.
Summary: A formal semantics for VHDL'93, including: signals, time, variables, and ports.
Subjects: VHDL
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Notes:  
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Jim Huggins / huggins@acm.org
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[an error occurred while processing this directive] URL: http://web.eecs.umich.edu/gasm/papers/vhdl93.html (page only)
last update: Wednesday, 14-Aug-2013 18:19:19 EDT