David Blaauw

Professor

David Blaauw

Professor

David Blaauw

Professor

University of Michigan
EECS Department
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Email:

Probabilistic Analysis of clock skew

Students:

Primary Contact

Aseem Agarwal <abagarwa@engin.umich.edu>

With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intra-die process variations and hence result in a very optimistic skew analysis. In this research, we present a statistical skew analysis method to model intra-die process variations. We first present a formal model of the statistical clock skew problem and then propose an algorithm which is based on propagation of joint probability distribution functions in a bottom up fashion in a clock tree. The analysis accounts for topological correlations between path delays and has linear run time with the size of the clock tree. The proposed method was tested on several large clock tree circuits, including a clock tree from a large industrial high-performance microprocessor. The results are compared with Monte Carlo simulation for accuracy comparison and demonstrate the need for statistical analysis of clock skew.


Publications:

Statistical Clock Skew Analysis Considering Intra-Die Process Variations

Aseem Agarwal, David Blaauw, Vladimir Zolotov, "Statistical Clock Skew Analysis Considering Intra-Die Process Variations," ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2003, pg. 914-921. ©IEEE

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Presentations

Statistical Performance Analysis
"Statistical Performance Analysis," Intel Timing Verification Seminar, Portland Oregon, June 2003

Statistical Analysis of Circuit Performance
"Statistical Analysis of Circuit Performance," Distinguished Lecture Series, University of Toronto, April 2003

Statistical Timing Analysis for VLSI Design
"Statistical Timing Analysis for VLSI Design," IBM Design Automation Professional Interest Seminar, IBM T. J. Watson Research Center, York Town, New York, September 2002

Variability in Chip-Level Performance Analysis
"Variability in Chip-Level Performance Analysis," Intel Performance Verification Seminar, Intel Inc., Haifa, Israel, May 2002