David Blaauw

Professor

David Blaauw

Professor

David Blaauw

Professor

University of Michigan
EECS Department
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Email:

Gate leakage Analysis and Reduction

Professors:

Students:

Primary Contact

Dongwoo Lee <dongwool@eecs.umich.edu>

Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. Also, gate oxide leakage current (Igate) has become comparable to subthreshold leakage (Isub) in 90nm technologies. In this research we address the growing issue of gate oxide leakage current (Igate) at the circuit level. We make two primary contributions. 
First, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both Igate and Isub. The interaction between Isub and Igate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of Igate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. 
As a second contribution, we propose a new method that uses a combined approach of sleep-state, threshold voltage (Vt) and gate oxide thickness (Tox) assignments in a dual-Vt and dual-Tox process to minimize both Isub and Igate. Using this method, total leakage current can be dramatically reduced since in a known state in standby mode, only certain transistors are responsible for leakage current and need to be considered for high-Vt or thick-Tox assignment. We formulate the optimization problem for simultaneous state, Vt and Tox assignments under delay constraints and propose two practical heuristics. We implemented and tested the proposed methods on a set of synthesized benchmark circuits. Results show an average leakage current reduction of 5-6X and 2-3X compared to previous approaches that only use state or state+Vt assignment, respectively, with small delay penalties.

Publications:

Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits

Dongwoo Lee, David Blaauw, Dennis Sylvester, "Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits," IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Volume 12,  Issue 2,  Feb. 2004, pg. 155 - 166. ©IEEE

File:


Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization

Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester, "Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization," ACM/IEEE Design Automation and Test in Europe Conference (DATE), Vol. 1, February 2004, pg. 494-499. ©IEEE

File:

Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage

Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester, "Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage," ACM/IEEE Design Automation Conference (DAC), June 2003, pg. 175-186 ©IEEE

File:
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current in Nanometer CMOS Design

Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester, "Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current in Nanometer CMOS Design," ACM/IEEE International Symposium on Quality Electronic Design (ISQED), March 2003, pg. 287-292 ©IEEE

File:

Presentations:

Standby Leakage Analysis and Optimization Methods for VLSI Design
"Standby Leakage Analysis and Optimization Methods for VLSI Design," full day tutorial with co-presenters Anirudh Devgan, Siva Narendra, Farid Najm, ACM/IEEE International Conference on Computer Aided Design (ICCAD), November 2003

Leakage Analysis and Reduction Methods
"Leakage Analysis and Reduction Methods," IBM Austin Research Laboratory, Austin, Texas, February 2003