David Blaauw

Professor

David Blaauw

Professor

David Blaauw

Professor

University of Michigan
EECS Department
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Email:

Drowsy Cache - Processor On-Chip L1 Cache Leakage Power Reduction


Professors:

Students:

Sponsor

DARPA

Primary Contact

Nam Sung Kim <kimns@eecs.umich.edu>

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. As feature sizes shrink, the dominant component of this power consumption will be leakage. However, during a fixed period of time the activity in a data cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large data caches by putting the cold cache lines into a state preserving, low-power sleep mode. In this paper we investigate policies and circuit techniques for implementing drowsy data caches. We show that with simple microarchitectural techniques, about 80% ~90% of the data cache lines can be maintained in a drowsy state without affecting performance by more than 0.6%, even though moving lines into and out of a drowsy state incurs a slight performance loss. According to our projections, in a 70nm CMOS process, drowsy data caches will be able to reduce the total leakage energy consumed in the caches by 60% ~75%. In addition, we extend the drowsy cache concept to reduce leakage power dissipation of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. In order to enable drowsy instruction caches, we propose a technique called cache sub-bank prediction, which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low leakage drowsy mode. This prediction technique reduces the negative performance impact by 78% compared to the no-prediction policy. Our technique works well even with small predictor sizes and enables a 75% reduction of leakage energy in a 32K byte instruction cache.

Publications:

Circuit and Microarchitectural Techniques Reducing Cache Leakage Power

Nam Sung Kim, Krisztian Flautner, David Blaauw and Trevor Mudge, "Circuit and Microarchitectural Techniques Reducing Cache Leakage Power," IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Volume 12,  Issue 2,  Feb. 2004, pg. 167 - 184. ©IEEE

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Drowsy Instruction Caches: Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-bank Prediction

Nam Sung Kim, Krisztian Flautner, David Blaauw, Trevor Mudge, "Drowsy Instruction Caches: Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-bank Prediction", ACM/IEEE International Symposium on Microarchitecture (MICRO), November 2002, pg. 219-230 ©IEEE

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Drowsy Caches: Simple Techniques for Reducing Leakage Power

Krisztian Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge, "Drowsy Caches: Simple Techniques for Reducing Leakage Power," ACM/IEEE International Symposium on Computer Architecture (ISCA), May 2002, pg. 148-157 ©IEEE

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