David Blaauw


David Blaauw


David Blaauw


University of Michigan
EECS Department
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617

Domino Razor: Adaptive Robustness Tuning for High Performance Domino Logic



Primary Contact

Bharan Giridhar <bharan@umich.edu>

A new domino design style is proposed that provides performance gains of up to 71% over conventional domino, and is demonstrated in a 32b multiplier in 65nm CMOS. The design dynamically tunes domino gates to trade surplus noise margins at nominal conditions for performance by detecting stability errors during runtime while guaranteeing correct operation. 

While many chips are constrained by power, speed critical circuit portions in a design continue to benefit from targeted use of a high performance logic design styles. Domino logic has been the mainstay for this purpose. However, increasing process variation has made conventional domino design more complex and less beneficial, forcing designers to revert back to static CMOS design. 

Margining the keeper for robustness under worst-case PVT conditions can result in a 32% delay increase. Increasing PVT sensitivities with process scaling and more frequent use of low voltage operation are expected to further increase these design margins. However, these margins can be reduced and traded for performance gains under typical PVT conditions. This motivates a new design style called Adaptive Robustness Tuning (ART) that shrinks robustness margins with minimal design overhead and enables performance gains of up to 34% using robustness speculation. Similar to recently proposed adaptive approaches, the robustness margins are reduced until functionality errors are detected. Failures are used to guide robustness tuning and are corrected to guarantee forward progress in computation. In addition to robustness speculation, ART also removes timing margins, increasing the total speed improvement. 

ART Domino was incorporated in a 32×32-bit multiplier in 65nm CMOS. The design is split into two pipe stages and four tunable voltage domains. With ART disabled, the multiplier runs at 890MHz (at 1.2V, 27ºC and consuming 184mW). Performance with ART improves to 1.192GHz (34% increase) by eliminating robustness margins at nominal PVT conditions. Measurement gains due to timing speculation at nominal temperature (27ºC) and voltage (1.2V) range from 20% to 33% compared to performance of the slowest die at 85ºC with 10% supply droop. Tuning robustness margins provides further gains (24% to 34%) resulting in measured total gains of 49% to 71% over conventionally margined designs.


Adaptive Robustness Tuning for High Performance Domino Logic

Bharan Giridhar, David Fick, Matthew Fojtik, Sudhir Satpathy, David Bull, Dennis Sylvester, David Blaauw, "Adaptive Robustness Tuning for High Performance Domino Logic", IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2011 ©IEEE