University of Michigan
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Error resilient circuit, hardware security, in-memory computing
I am currently working on a new type of Razor design, that detects and corrects the timing error. The design is targeting at smaller overhead and larger timing speculation window. It will be implemented on a complete, commercial processor without knowing its internal architecture, which shows automated capability of this technique.