David Blaauw

Professor

David Blaauw

Professor

David Blaauw

Professor

University of Michigan
EECS Department
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Email:

Alumni Ph.D.

Sudhir Satpathy
Contact Information:

4849 Computer Science Building
2260 Hayward
Ann Arbor, MI 48109-2122
Ph: (734) 763-3344
sudhirks AT umich DOT edu

Research Interest:

High Performance and Low Power On-Die Switch FabricsĀ 
Circuit Techniques for on-chip signaling

Current Research:

Increasing power density with technology scaling has halted the trend of frequency enhancement in today’s chips. This has led designers prefer multi-core architectures over complex monolithic processors. Although processing units are getting smaller and simpler, the dramatic rise of their count on a single die has made the interconnect fabric increasingly complex. These fabrics have become a bottleneck in improving overall system efficiency. As a result, the design paradigm for multi-core chips is gradually shifting from a core-centric architecture towards an interconnect-centric architecture, where system efficiency is limited by the fabric rather than the processing ability of any individual core. My research is based on three novel and synergistic circuit techniques to improve scalability of switch fabrics to make on die integration of thousands of cores feasible. 1) A matrix topology is proposed for designing a fully connected switch fabric that re-uses output buses for programming, and stores shuffle configurations at cross points. This significantly reduces routing congestion, lowers area/power, and improves performance. Silicon measurements demonstrate 47% energy savings in a 64-lane SIMD processor fabricated in 65nm CMOS over a conventional implementation. 2) A novel approach to handle high radix arbitration along with data routing is proposed. It optimally uses existing cross-bar interconnect resources without requiring any additional overhead. Bandwidth exceeding 2Tb/s is recorded in a test prototype fabricated in 65nm. 3) Building on the later, a new circuit topology to manage and update priority adaptively within the switch fabric without incurring additional delay or area is then proposed. Several assist circuit techniques, such as a thyristor based sense amplifier and self regenerating bidirectional repeaters are also used for high speed energy efficient signaling to and from the switch fabric to improve overall routing efficiency.