University of Michigan
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Analysis of low power VLSI. Analysis and minimization of leakage current. Static timing analysis.
My current research focuses on analysis and minimization of leakage power in current and future technologies. We propose a new leakage minimization technique for the subthreshold leakage current (Isub) in standby mode. This method combines the input state dependence of leakage current of a gate and dual Vt technology. In addition to the subthreshold leakage current, the gate tunneling leakage current (Igate) should be considered in the total leakage current due to increased amount of Igate in recent technologies. Before proposing a Igate minimization technique, a new circuit level estimation method of Igate is developed. Based on this analysis of Igate, we propose a new approach for the total leakage current minimization including both Isub and Igate. In addition to input state and Vt, dual oxide thickness is assigned for the Igate reduction.
As a future work, the analysis and minimization of leakage current in standby mode will be extended to that of runtime mode.