David Blaauw

Professor

David Blaauw

Professor

David Blaauw

Professor

University of Michigan
EECS Department
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Email:

Alumni Ph.D.

Yejoong Kim
Contact Information:

2435 EECS
1301 Beal Avenue
Ann Arbor, MI 48109-2122
yejoong@umich.edu

CV:  [click here]

Research Interest:

Low-power high-performance VLSI circuit design 
mm3-scale wireless sensor nodes

Current Research:

Sequential Elements 
Near-threshold computing (NTC) is an attractive solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS. However, in NTC, Process/Voltage/Temperature (PVT) variations become a critical concern for circuit robustness, and a correct operation at one PVT corner does not necessarily guarantee functional correctness at other PVT corners. The design of sequential elements is not an exception, and it is well known that they have a strong sensitivity to process variations in NTC, which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have static operation, contention-free transitions, single-phase clocking, and minimum or no area penalty compared to conventional ones. 
My recent research presented a new flip-flop, referred to as S2CFF (Static Single-phase Contention-free Flip-Flop) that meets all the requirements mentioned above; it is static, completely contention-free, and uses single-phase clocking. It has the same device count as a TGFF, with only a 7\% increase in layout size that corresponds to one poly-pitch increase in 45nm technology where fixed poly-pitch is enforced. You can find detailed information in the following paper:  Y. Kim et al., A Static Contention-Free Single-Phase-Clocked 24T Flip-Flop in 45nm for Low-Power Applications, ISSCC 2014. 

Robust SRAM Design 
The traditional 6T SRAM design has 'robustness issues' at low supply voltages, and the ever-decreasing technology dimension causes large variations even at the nominal voltage. Various alternatives including 8T, 10T SRAMs have been investigated to overcome these issues at the cost of area overheads. Generally 8T bitcells have 30~70% larger bitcell size compared to 6T bitcells, but volume-limited applications such as mm3-scale sensor nodes cannot afford it. I'm currently working on a new 7T SRAM design that minimizes the area overhead but still provides the same robustness as 8T, 10T SRAMs.