David Blaauw

Professor

David Blaauw

Professor

David Blaauw

Professor

University of Michigan
EECS Department
Electrical & Computer Engineering
1301 Beal Ave., 2417C EECS
Ann Arbor, MI 48109
Tel: 734 763 4526
Fax: 734 763-4617
Email:

Alumni Ph.D.

Bharan Giridhar
Contact Information:

2435 EECS
, MI 
bharan@umich.edu

Research Interest:

Adaptive computing; circuit techniques for reliability, high performance and low power; non-volatile memories 

Projects: 
• Very high MTBF synchronizer design (current) 
• Non-volatile memory design for exascale machines (current) 
• Adaptive robustness tuning for high performance domino logic 
   - Proposed a domino design style to dynamically trade surplus noise margins at nominal conditions for performance by detecting stability errors while guaranteeing forward progress 
   - The prototype was fabricated in 65nm CMOS and tested to show performance boost of up to 71% over static CMOS 
• A multi-stage temperature compensated timer for ultra-low power wireless sensor node synchronization 
   - Worked on a low jitter and ultra-low power timer based on gate-leakage for measuring long-term synchronization period for wireless sensor nodes 
   - The prototype was fabricated and tested in a 130nm CMOS process and consumed ~660pW of power 
• Centipede: A near-threshold 7-layer 3D system with 128 ARM Cortex-M3 cores and 256MB of DRAM 
   - Worked on the design and 3D integration aware layout of custom 8T-SRAM based caches 
   - Designed and implemented a glitch free clock generation scheme for 2-core and 4-core mode operation 
   - Designed and implemented a clock tree alignment sensor for post-silicon clock alignment between DRAM bus and caches and cores spanning multiple voltage domains 
   - The prototype was fabricated and tested in a 130nm CMOS process