David Blaauw received his B.S. from Duke University in 1986 and his Ph.D. from the University of Illinois, Urbana, in 1991. From 1993 until August 2001, he worked for Motorola, Inc. in Austin, TX, where he was the manager of the High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan where he is currently a full Professor. His work has focused on VLSI design with particular emphasis on adaptive and low power design.
In the area of adaptive design, Blaauw introduced a new approach called Razor in 2003 (MICRO) where processor chips automatically tune their frequency or supply voltage to the point of failure, thereby eliminating wasteful design margins. By adding low-overhead delay error detection and correction circuits, the Razor approach allows the processor to be tuned to the point where failures start to occur (which are automatically corrected) indicating that all margins are removed. As the chip experiences different environmental conditions, such as temperature and supply voltage changes or aging effects, Razor automatically tracks the innate performance of the design by maintaining a low error rate. Razor was implemented in several test chips showing as much as 50% power reduction and 30% performance improvement and has spawned significant further research in related approaches by industry and academic researchers. In addition, Blaauw has investigated other areas of adaptive design, such as methods for in situ detection and management of oxide-breakdown and NBTI degradation.
In the area of low power design, Blaauw introduced the concept of the "energy optimal voltage" (Vopt) in 2004 (DAC) together with his student Bo Zhai and colleague Dennis Sylvester. At the Vopt voltage, energy per operation reaches a minimum and further reduction of the supply voltage increase leakage energy more quickly than dynamic energy reduces. Typically, Vopt lies below the threshold voltage, leading to the need for subthreshold design. Blaauw's and Sylvester's research team spend the following years developing ultra-low power sensor systems using subthreshold design. this lead to numerous publications, ranging from new, ultra-low voltage SRAM design, subthreshold processor architectures, timers, new subthreshold power gating methods, low power radios, power management, DC-DC conversion, analog to digital conversion (ADC), level shifters, and energy harvesting. This work culminated in 2011 (ISSCC) in the publication of in the worlds first mm-scale, complete sensor node with a volume of 1.5mm-cube, including radio, battery for 1 month of operation, pressure sensor, processor, memory, and solar cells which extend operation indefinitely. They continue the development of ultra-small sensor nodes for new applications domains through new circuit techniques.
At the high end, Blaauw has applied low power techniques to throughput limited computing found in data centers. Together with Prof. Mudge and Sylvester, he introduced the concept of "near threshold design" (NTC) in 2007 (ISLPED). For throughput constrained, parallelizable applications, NTC finds that the optimal trade-off between the energy efficiency gained through low voltage operation and the associated performance loss lies at a supply voltage that is ~200mV above the threshold voltage. This has lead to new investigations by their research team into low voltage design for chip multiprocessors, including new high radix routers to connect chip multiprocessors with memory, and investigation into 3D design.